A data signal is sometimes transmitted without a clock signal (e.g., a non-return to zero (NRZ) signal). NRZ signals are advantageous in that they require only half the bandwidth necessary to transmit both a data signal and a clock signal. However, a clock signal is still useful to sample the data signal and recover the data.
One way to sample the data signal is to use a recovered clock signal. A clock signal may be recovered by generating a reference clock signal, and then phase-aligning and frequency-aligning the generated clock signal to the data signal. This is often referred to as clock and data recovery (CDR). A continuous-rate CDR is a CDR that can operate over a wide range of data rates.
A phase-locked loop (PLL) clock recovery system may be used to recover a clock signal. Generally, a PLL detects the phase difference and frequency difference between the received NRZ and a reference clock signal, and modulates the source of the reference signal (e.g., a voltage controlled oscillator (VCO)) to bring it into the same phase and frequency as the NRZ. An example of a PLL-implemented CDR system is found in an article entitled, “A Self Correcting Clock Recovery Circuit”, Journal of Lightwave Technology, Vol. LT-3, No. 6, December 1985, by Charles R. Hogge, Jr., which is incorporated by reference in its entirety.
A delay-locked loop (DLL) clock recovery system may also be used to recover a clock signal. One difference between a DLL and a PLL is that the DLL does not adjust a VCO. Instead, the DLL compares the phase of an output to the phase of an input to generate an error signal, which is fed back to control delay elements in the DLL. The error signal goes, essentially, to zero, when the tunable delay aligns the phase of the output of the DLL to the phase of the input.
PLLs and DLLs may be combined into a dual loop D/PLL architecture. An example of an analog implementation of a D/PLL CDR system is found in U.S. Pat. No. 5,036,298, “Clock Recovery Circuit with Jitter Peaking,” assigned to Analog Devices, Inc., which is incorporated by reference in its entirety. Among other advantages, D/PLL systems permit separate jitter-tolerance (JTOL) and jitter-transfer (JTRAN) bandwidths, each optimized for manufacturing robustness. JTOL is a measure of the ability of a PLL to operate properly (i.e., remain in lock in the presence of jitter of various magnitudes at different frequencies) when jitter is applied to the source data signal. JTRAN bandwidth is measure of the magnitude of the jitter at an output of a device with respect to the magnitude of jitter at an input.
Decoupling JTRAN from JTOL leads to a signal conditioner (i.e., a device that converts one type of electronic signal into a another type of signal) in which there can be substantially less jitter at the output of the signal conditioner relative to the input. This eases the jitter tolerance requirements of subsequent clock and data recovery (CDR) circuits in a host system, e.g., 1 UIpp of jitter at 8 MHz on the input is attenuated to 0.15 UIpp at the output for a D/PLL with a jitter transfer bandwidth of 1.2 MHz.
FIG. 1 illustrates an analog D/PLL that is part of a prior art continuous-rate CDR system. The CDR system in FIG. 1 aligns both frequency and phase, however, only phase alignment is relevant to this disclosure. The prior art D/PLL includes a PLL 1 and a DLL 2. The PLL 1 includes the Phase Detector 8, the Analog Charge Pump 9, the Phase Capacitor (CP) 10, the VCO 11 and the Divider 12. The VCO 11 includes a fine tune voltage control KVCO and a coarse tune voltage control OCKVCO, which are known to those of ordinary skill in the art. The DLL 2 includes the Phase Shifter 7, the Phase Detector 8, the Analog Charge Pump 9, and the CP 10.
The output of the Phase Shifter 7 is input to the Phase Detector 8, which can be either linear or binary. High-frequency JTOL has, for example, a 3 dB bandwidth for a linear phase detector, and is slew rate limited on phase for a binary phase detector. Decoupled JTRAN and JTOL bandwidths are maintained regardless of whether the phase detector is linear or binary. Moreover, the JTRAN is identical for either a linear or binary phase detector, which is not the case for a single-loop PLL.
Up/down information from the Phase Detector 8 is applied to the charge pump PhCP 13. Ideally, an analog charge pump is a perfect integrator with a pole at DC. However, circuit imperfections such as leakage currents and finite output device impedances make the charge pump a leaky integrator. Leaky integrators lead to steady state errors at the output of the Phase Detector 8. Steady state errors in CDRs result in static phase offset, where the sampling is no longer in the middle of the data eye. Another source of static phase offset in linear phase detectors is mismatch between pump up and pump down currents in the charge pump PhCP 9. This mismatch is not problematic in a binary phase detector. Leaky integrators may also cause the D/PLL to lose frequency lock in the presence of a long sequence of consecutive identical digits.
The charge pump PhCP 9 and capacitor Cp 10 voltage controls the group delay of the Phase Shifter 7. This same charge pump voltage is also applied to a varactor port with gain KVCO on the VCO 11. The varactor port with gain KVCO is part of the PLL 1. The Divider 12 is typically a power of 2 (i.e., 2N), whose value is determined during rate acquisition according to methods known to those of ordinary skill in the art.
Because the charge pump PhCP 9 and capacitor Cp 10 are shared by the PLL 1 and DLL 2, careful circuit design is taken to guarantee that the gain of the PLL 1 goes to 0 before the gain of the DLL 2 goes to 0. Otherwise, the system risks going unstable.
The VCO 11 has multiple tunable parameters not illustrated in FIG. 1. Only the parameters that are manipulated by the loop filter are shown in FIG. 1. Two VCO controls shown are a fine tune varactor with gain KVCO and a coarse tune varactor whose gain is scaled by a factor Oc relative to KVCO (i.e., OcKVCO).
The coarse tune control voltage on capacitor CF 6 is set during frequency acquisition by a separate charge pump FCP 4. This particular figure shows lock-to-reference frequency acquisition, although in other embodiments frequency acquisition technique locks on data. Once frequency acquisition is completed, the charge pump FCP 4 is disabled and a drift or leakage compensation is enabled to adjust the voltage on the capacitor CF 6.
Feedback for drift compensation includes an integrator (i.e., Gm 5 and CF 6) which controls the coarse tune varactor. Drift compensation keeps a voltage on a fine tune varactor in the middle of its tuning range. A zero formed by summing the gains of the fine tune path and drift compensation path should be in the low Hz range to avoid excessive peaking in the jitter transfer frequency response. One consequence of having such a low bandwidth is that capacitor CF 6 must be a large off-chip capacitor. In fact, capacitor CF operates in the milli-farad range, which is very large device. Thus, there is a need for a smaller, on-board drift compensation circuit.
The Phase Shifter 7 implements a variable delay analog first-in-first-out (FIFO) on data. The Phase Shifter 7 implementation is limited because it has a restricted range of tunable delays, it is not readily amenable to covering multiple octaves of data rates, and its bandwidth must change with frequency to maintain the same gain and phase shift range. Continuous-rate CDRs covering multiple octaves generally have to employ different phase shifters for ranges of octaves, as well as multiple stages of phase shifters within each range. Thus, there is also a need for a device with as close to limitless phase shift delays as possible; and amenable to covering multiple octaves of data rates without resorting to different devices for different octaves.
A need therefore exists for a clock recovery circuit, with programmable delay and bandwidth, without large on (and off) chip analog components, and that is capable of operating over multiple octaves. Other disadvantages of the prior art may also be overcome by the present invention.